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october 2008 rev 12 1/52 1 nandxxxxnx large page nand flash memory and low power sdram, 1.8/2.6 v mcp and pop features n mcp (multichip package) and pop (package on package) ? nand flash memory ? 1-, 2-, 4-, 2x2-gbit large page size nand flash memory ? 256-, 512-, 2x512-, 128+256/512-mbit or 1-gbit (x16/x32) sdr/ddr lpsdram n temperature range: -30 up to 85 c n supply voltage ? nand flash: v ddf = 1.7-1.95 v or 2.5-3.6 v ? lpsdram: v ddd = v ddqd = 1.7-1.95 v n electronic signature n ecopack ? packages flash memory n nand interface ? x8 or x16 bus width ? multiplexed address/data n page size ? x8 device: (2048 + 64 spare) bytes ? x16 device: (1024 + 32 spare) words n block size ? x8 device: (128k + 4k spare) bytes ? x16 device: (64k + 2k spare) words n page read/program ? random access: 25 s (max) ? sequential access: 25/30 ns (min) ? page program time: 200 s (typ) n copy back program mode n fast block erase: 1.5/2 ms (typ) n chip enable ?don?t care? n status register n data integrity ? 100 000 program/erase cycles ? 10 years data retention single or double data rate lpsdram n interface: x16/32 bus width n deep power-down mode n 1.8 v lvcmos interface n quad internal banks controlled by ba0, ba1 n wrap sequence: sequential/interleaved n automatic and controlled precharge n auto refresh and self refresh ? 8192 or 4096 (for 128 mbits) refresh cycles/64 ms ? programmable partial array self refresh ? auto temperature compensated self refresh table 1. device summary nandxxxxnx nanda0r3n0 nanda8r3n0 nanda9r3nx nanda9r4nx nanda9wxn1 nandb0r3n0 nandbar3nx nandbar4nx nandb1r3n0 nandb9r3n0 nandb9r4nx nandc9r4n0 nandbaw4n1 nandcaw4n1 nandcbr4n3 nandc3r4n5 nandd3r4n5 nanddbr3n5 fbga tfbga107 10.5 13 1.2 mm tfbga137 10.5 x 13 x 1.2 mm lfbga137 10.5 x 13 x 1.4 mm tfbga149 10 13.5 1.2 mm vfbga160 15 x 15 x 1 mm vfbga152 14 x 14 x 0.9 mm tfbga152 1414 1.1 mm tfbga152 14 14 1.2 mm tfbga128 12 x 12 x 1.1 mm fbga www.numonyx.com
contents nandxxxxnx 2/52 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 flash memory inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 flash memory inputs/outputs (i/o8-i/o15) . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 flash memory address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 flash memory command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . 25 2.5 flash memory chip enable (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.6 flash memory read enable (r ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.7 flash memory write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 flash memory write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.9 flash memory ready/busy (rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.10 flash memory v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.11 lpsdram address inputs (a0-ax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.12 lpsdram bank select address inputs (ba0-ba1) . . . . . . . . . . . . . . . . . 26 2.13 lpsdram data inputs/outputs (dq0-dq31) . . . . . . . . . . . . . . . . . . . . . . 27 2.14 lpsdram chip select (e d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.15 lpsdram column address strobe (cas ) . . . . . . . . . . . . . . . . . . . . . . . 27 2.16 lpsdram row address strobe (ras ) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.17 lpsdram write enable (w d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.18 lpsdram clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.19 lpsdram clock input (k ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.20 lpsdram clock enable (ke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.21 lpsdram lower/upper data input/output mask (dqm0 to dqm3) . . . . . 28 2.22 dqs0 to dqs3 input/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.23 lower/upper data read/write strobe input/output (ldqs, udqs) . . . . 28 2.24 lpsdram v ddd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.25 lpsdram v ddqd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.26 ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.26.1 nandxxxxnx devices delivered in tfbga107/137/149 packages . . . . 29 2.26.2 nandxxxxnx delivered in tfbga128/152 and vfbga160 packages . 29
nandxxxxnx contents 3/52 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
list of tables nandxxxxnx 4/52 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5. tfbga107 10.5 13 mm - 10 14 active ball array, 0.80 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6. tfbga128 - 2-row perimeter matrix 2r18 18, 12 12 mm, 0.65 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 7. tfbga137 10.5 x 13 mm - 10 x 15-13 active ball array, 0.80 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8. lfbga137 10.5 x 13 x 1.4 mm - 10 x 15-13 active ball array, 0.80 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 9. tfbga149 10 13.5 mm - 12 16 active ball array, 0.80 mm pitch, mechanical data. . . 43 table 10. tfbga152, 2-row perimeter matrix 2r21 x 21, 14 x 14 x 1.1 mm, 0.65 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 11. tfbga152, 2-row perimeter matrix 2r 21 x 21, 14 x 14 x 0.9 mm, 0.65 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. tfbga152, 2-row perimeter matrix 2r21 x 21, 14 14 x 1.2 mm, 0.65 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13. vfbga160 15 15 x 1 mm, 0.65 mm pitch, mechanical data . . . . . . . . . . . . . . . . . . . . . . 47 table 14. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
nandxxxxnx list of figures 5/52 list of figures figure 1. block diagram for tfbga107, tfbga137, and tfbga149 packages . . . . . . . . . . . . . . . 11 figure 2. block diagram for lfbga137 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. block diagram for tfbga128, tfbga152 (nanda8r3n0, nanda9r3n0, nandbar3n, nandb9r3n0), vfbg a152, and vfbga160 packages . . . . . . . . . . . . . 13 figure 4. block diagram for tfbga152 package (nandbar3n0, nandb0r3n0, nandb1r3n0, nanda0r3n0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. tfbga107 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. tfbga128 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. tfbga137 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. lfbga137 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. tfbga149 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. tfbga152 connections - nanda8r3n0, nanda9r3n0, nandb9r3n0 (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. tfbga152 connections - nandbar3n0, nandb0r3n0, nandb1r3n0, nanda0r3n0 (top view through packag e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. tfbga152 (nandbar3n1) and vfbga152 (nandbar4n5) connections - (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. vfbga160 connections - nandbar4n2 (top view through package) . . . . . . . . . . . . . . . 24 figure 14. functional block diagram for tfbga107, tfbga137, tfbga149 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. functional block diagram for lfbga137 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16. functional block diagram for tfbga128 (nanda9r3n0, nandb9r3n0), tfbga152 (nanda8r3n0, nanda9r3n0, nandbar3n1, nandb9r3n0), vfbga152 (nandbar4n5), and vfbga160 packages. . . . . . . . . . . . 33 figure 17. functional block diagram for tfbga152 (nandbar3n0, nandb0r3n0, nandb1r3n0, nanda0r3n0) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18. functional block diagram for tfbga128 (nandb ar3n6) package . . . . . . . . . . . . . . . . . 35 figure 19. tfbga107 10.5 13 mm - 10 14 active ball array, 0.80 mm pitch, package outline . . . 37 figure 20. tfbga128 - 2-row perimeter matrix 2r18 18, 12 12 mm, 0.65 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 21. tfbga137 10.5 x 13 x 1.2 mm - 10 x 15-13 active ball array, 0.80 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 22. lfbga137 10.5 x 13 x 1.4 mm - 10 x 15-13 active ball array, 0.80 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 23. tfbga149 10 13.5 mm - 12 16 active ball array, 0.80 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 24. tfbga152, 2-row perimeter matrix 2r 21 x 21, 14 x 14 x 1.1 mm, 0.65 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 25. vfbga152, 2-row perimeter matrix 2r 21 x 21, 14 x 14 x 0.9 mm, 0.65 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 26. tfbga152, 2-row perimeter matrix 2r21 x 21, 14 14 x 1.2 mm, 0.65 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 27. vfbga160 15 15 x 1 mm, 0.65 mm pitch, pack age outline . . . . . . . . . . . . . . . . . . . . . . 47
description nandxxxxnx 6/52 1 description the nandxxxxnx devices combine multiple memory devices in a multichip package or a package-on-package solution that includes: l 1.8/2.6 v supply 1- or 2-gbit (x8/x16) or 4-gb it (x16), or 1.8 v supply 2 x 2-gbit (16), nand flash memories (nand01gwxb2b, nand01grxb2b, nand01grxb2c, nand02grxb2c, nand02grxb2d, nand04gxxb2d) l 128-mbit (x16) sdr (single data rate ) lpsdram (m65ka128aj) + 256-mbit (x16) sdr lpsdram (m65ka256aj), or l 128-mbit (x16) sdr lpsdram (m65ka128 aj) + 512-mbit (x16) sdr lpsdram (m65ka512ac), or l 256-mbit (x16) sdr lpsdram (m65ka256ag), or l 512-mbit (x16) sdr lpsdra m (m65ka512ab, or m65ka512ac, or m65ka512ah, or m65ka512am), or l 2 x 512-mbit (x16) sdr lpsdrams (m65ka512ab, or m65ka512am, or m65ka512ac, or m65ka512aj), or l 512-mbit (x32) sdr lpsdram (m65kc512ab or m65kc512ac), or l 1-gbit (x32) sdr lpsdram (m65kc001aj), or l 512-mbit (x16) ddr (double data rate) lpsdram (m65kg512ab, or m65kg512ah, or m65kg512am, or m65kg512ac), or l 512-mbit (x32) ddr lpsdram (m65kd512ac), or l 1-gbit (x16) ddr lpsdram (m65kg001aj), or l 1-gbit (x32) ddr lpsdram (m65kd001aj) l 2 x 1-gbit (x32) ddr lpsdram (m65kd001aj). the nand flash memory and lpsdram compone nts have separate power supplies. they also have separate control, address and input/output signals, which allows simultaneous access to both devices at any moment. they may or not share the same grounds, depending on the package in which they are offered. they are distinguished by a chip enable input, e f , for the nand flash memory and a chip select, e d , for the lpsdram. see figure 1: block diagram for tfbga107, tfbga137, and tfbga149 packages , figure 3: block diagram for tfbga128, tfbga152 (nanda8r3n0, nanda9r3n0, nandbar 3n, nandb9r3n0), vfbga152, and vfbga160 packages , figure 4: block diagram for tfbga1 52 package (nandbar3n0, nandb0r3n0, nandb1r3n0, nanda0r3n0) , and table 3: signal names for an overview of the signals asso ciated with each component. this datasheet should be read in conjunction with the slc large page nand flash datasheets (nand01g-b2b_nand02g-b2c, nand01g-b2c, nand02g-b2d, and nand04g-b2d_nand08g-bxc) and l psdram datasheets (m65ka256ag, m65ka512ab, m65ka512ac, m65kg 512ab, m65kc512ab, m65kc512ac, m65kd512ac, m65kaxxxaj, m65ka512ah, m65kg512ah, m65kgxxxaj, m65kaxxxam, m65kcxxxaj, m65kdxxxaj, m6 5kgxxxam, and m65kg512ac).
nandxxxxnx description 7/52 the nandxxxxnx devices are ava ilable with a 1.8 v or 2.6 v voltage supply and are offered in the following packages as shown in table 2: product list : l tfbga107 (10.5 13 1.2 mm) l tfbga137 (10.5 x 13 x 1.2 mm) l lfbga137 (10.5 x 13 x 1.4 mm) l tfbga152 (14 14 1.1 mm) and tfbga152 (14 14 1.2 mm) l vfbga152 (14 x 14 x 0.9 mm) l tfbga149 (10 13.5 1.2 mm) l tfbga128 (12 x 12 x 1.1 mm) l vfbga160 (15 x 15 x 1 mm) the memories are supplied with all the nand flash memory bits erased (set to ?1?).
description nandxxxxnx 8/52 table 2. product list reference part number nand product datasheet lpsdram product (1)(2) lpsdram name package nanda0r3n0 nanda0r3n0 1 gbit (x8) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 128 + 512 mbits (x16), 1.8 v, 133 mhz m65ka128aj + m65ka512ac tfbga152 nand01g- b2c nanda8r3n0 nanda8r3n0 1 gbit (x8) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 256 mbits (x16), 1.8 v, 133 mhz m65ka256ag tfbga152 nanda9r3nx nanda9r3n0 1 gbit (x8) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 512 mbits (x16), 1.8 v, 133 mhz m65ka512ab or m65ka512ah tfbga107 nand01g- b2c m65ka512ab tfbga152 m65ka512ac tfbga128 nanda9r3n1 1gbit (x8) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 512 mbits (x32) 1.8 v, 133 mhz m65kc512ac tfbga137 nanda9r3n2 1gbit (x8) - 1.8 v ddr 512 mbits (x16) 1.8 v, 133 mhz m65kg512ah tfbga107 nanda9r3n3 1gbit (x8) - 1.8 v ddr 512 mbits (x32) 1.8 v, 133 mhz m65kd512ac tfbga137 nanda9r3n6 1gbit (x8) - 1.8 v nand01g- b2c sdr 512 mbits (x16) 1.8 v, 166 mhz m65ka512am tfbga107 nanda9r4nx nanda9r4n0 1 gbit (x16) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 512 mbits (x16), 1.8 v, 133 mhz m65ka512ab or m65ka512ah tfbga149 nanda9r4n1 1 gbit (x16) - 1.8 v sdr 512 mbits (x32) 1.8 v, 133 mhz m65kc512ac tfbga137 nanda9r4n2 1 gbit (x16) - 1.8 v ddr 512 mbits (x16), 1.8 v, 133 mhz m65kg512ab or m65kg512ah tfbga149 nanda9r4n3 1 gbit (x16) - 1.8 v ddr 512 mbits (x32), 1.8 v, 133 mhz m65kd512ac tfbga137 nanda9r4n4 1 gbit (x16) - 1.8 v nand01g- b2c ddr 512 mbits (x16), 1.8 v, 166 mhz m65kg512am tfbga149 nanda9r4n6 1 gbit (x16) - 1.8 v sdr 512 mbits (x16), 1.8 v, 166 mhz m65ka512am tfbga149
nandxxxxnx description 9/52 nanda9wxn1 nanda9w3n1 1 gbit (x8) - 2.6 v nand01g- b2b_nand0 2g-b2c sdr 512 mbits (x32) 1.8 v, 133 mhz m65kc512ab tfbga137 nanda9w4n1 1 gbit (x16) - 2.6 v m65kc512ac nandb0r3n0 nandb0r3n0 2 gbits (x8) - 1.8 v nand02g- b2d sdr 128 + 512 mbits (x16) 1.8 v, 133 mhz m65ka128aj + m65ka512ac tfbga152 nandbar3nx nandbar3n1 2 gbits (x8) - 1.8 v nand02g- b2d sdr 1 gbit (x 32) [2 x 512 mbits x16], 1.8 v, 133 mhz m65ka512ab tfbga152 nandbar3n6 2 gbits (x8) - 1.8 v sdr 1 gbit (x32) [2 x 512 mbits x16], 1.8 v, 166 mhz m65ka512am tfbga128 nandbar4nx nandbar4n0 2 gbits (x16) - 1.8 v nand02g- b2d sdr 1 gbit (x16), 1.8 v, 133 mhz m65ka001aj tfbga149 nandbar4n1 2 gbits (x16)- 1.8 v sdr 1 gbit (x32)(2 x 512 mbits x16), 1.8 v, 166 mhz m65ka512aj tfbga137 nandbar4n2 2 gbits (x16)- 1.8 v ddr 1 gbit (x16), 1.8 v, 133 mhz m65kg001aj vfbga160 tfbga149 nandbar4n5 2 gbits (x16)- 1.8 v ddr 1 gbit (x32), 1.8 v, 166 mhz m65kd001aj tfbga137 vfbga152 nandbar4n7 2 gbits (x16)- 1.8 v sdr 1 gbit (x32), 1.8 v, 166 mhz m65kc001aj tfbga137 nandbaw4n1 nandbaw4n1 2 gbits (x16)- 2.6 v nand02g- b2d sdr 1 gbit (x32), 1.8 v, 133 mhz m65ka512aj tfbga137 tbd tbd 2 gbits (x8)- 1.8 v nand02g- b2d ddr 1 gbit (x16), 1.8 v m65kg001am tfbga137 nandb1r3n0 nandb1r3n0 2 gbits (x8) - 1.8 v nand02g- b2d sdr 128 + 256 mbits (x16) 1.8 v, 133 mhz m65ka128aj + m65ka256aj tfbga152 nandb9r3n0 nandb9r3n0 2 gbits (x8) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 512 mbits (x16), 1.8 v, 133 mhz m65ka512ab tfbga128 nand02g_b 2d m65ka512ac tfbga152 table 2. product list (continued)
description nandxxxxnx 10/52 nandb9r4nx nandb9r4n0 2 gbits (x16) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 512 mbits (x16), 1.8 v, 133 mhz m65ka512ab tfbga149 nandb9r4n2 2 gbits (x16) - 1.8 v nand02g_b 2d ddr 512 mbits (x16), 1.8 v, 133 mhz m65kg512ac tfbga149 nandb9r4n5 2 gbits (x16) - 1.8 v nand01g- b2b_nand0 2g-b2c ddr 512 mbits (x32) 1.8 v, 166 mhz m56kd512ac tfbga137 nandc3r4n5 nandc3r4n5 4 gbits (x16) - 1.8 v nand04gr4 b2d ddr 1g (x32) 2x 1g ddr (x16) m65kd001am m65kg001am lfbga137 nandcaw4n1 nandcaw4n1 4 gbits (x16)- 2.6 v nand04g- b2d_nand0 8g-bxc sdr 1 gbit (x32)(2 x 512 mbits x16), 1.8 v, 133 mhz m65ka512aj tfbga137 nandcbr4n3 nandcbr4n3 4 gbits (x16)- 1.8 v nand04g- b2d_nand0 8g-bxc ddr 2 gbits (x32)(2 x 1 gbit x32), 1.8 v, 133 mhz m65kd001aj lfbga137 nandc9r4n0 nandc9r4n0 2x2 gbits (x16) - 1.8 v nand01g- b2b_nand0 2g-b2c sdr 512 mbits (x16), 1.8 v, 133 mhz m65ka512ab tfbga149 nandd3r4n5 nandd3r4n5 2x4 gbits (x16) - 1.8 v nand08gr4 b2c ddr 1g (x32) 2x 1g ddr (x16) m65kd001am m65kg001am lfbga137 nanddbr3n5 nanddbr3n5 2x4 gbits (x16) - 1.8 v nand08gr4 b2c 2x 1g ddr (x16) m65kg001am lfbga137 1. sdr = single data rate. 2. ddr = double data rate. table 2. product list (continued)
nandxxxxnx description 11/52 figure 1. block diagram for tfbga10 7, tfbga137, and tfbga149 packages 1. only available in mcp with ddr x32. 2. only available in mcp with ddr. 3. only available in mcp with sdr/ddr x32. 4. only available in mcp with ddr x16. 5. x = 12 (width bus dram y = 13 bits) except for nandbar4n0 and nandbar4n2, which have x = 13 (width bus dram y = 14 bits). ai14289 y a0-ax (5) dqm0 k v ddf dq0-dq15, x16 dq16-dq31, x16/x32 nandxxxxnx e f w f al 2 ba0-ba1 ras r v ddqd v ddd rb i/o8-i/o15, x16 v ssf i/o0-i/o7, x8/x16 cl ke e d w d cas dqm2 (3) dqm1 dqm3 (3) wp k (2) dqs0-dqs3 (1) udqs (4) ldqs (4) v ssd v ssqd
description nandxxxxnx 12/52 figure 2. block diagram for lfbga137 package ni3065 y a0-a12 dqm0 k v ddf dq0-dq15 dq16-dq31 nandxxxxnx e f w f al 2 ba0-ba1 ras r v ddqd v ddd rb i/o8-i/o15 v ssf i/o0-i/o7 cl ke 1 e d1 w d cas dqm2 dqm1 dqm3 wp k dqs0-dqs3 v ssd v ssqd ke 2 e d2
nandxxxxnx description 13/52 figure 3. block diagram for tfbga12 8, tfbga152 (nanda8r3n0, nanda9r3n0, nandbar3n, nandb9r3n0), vfbga 152, and vfbga160 packages 1. only available in pop with ddr. 2. only available in pop with ddrx16. 3. only available in pop with sdr/ddr x32. 4. x = 12 (width bus dram y = 13 bits) except fo r nandbar4n2, which has x = 13 (width bus dram y = 14 bits). 5. ke 2 and e d2 are only used for the possible second lpsdram (nandbar3n6). ai14290 y a0-ax (4) dqm0 k v ddf dq0-dq15 nandxxxxnx e f w f al 2 ba0-ba1 ras r v ddqd v ddd rb i/o8-i/o15, x16 v ss i/o0-i/o7, x8/x16 cl ke 1 e d1 w d cas dqm2 (3) dqm1 dqm3 (3) wp k (1) dq16-dq31 (3) udqs (2) ldqs (2) e d2 (5) ke 2 (5)
description nandxxxxnx 14/52 figure 4. block diagram for tfbga15 2 package (nandbar3n0, nandb0r3n0, nandb1r3n0, nanda0r3n0) 1. d1-x signals are related to the 128-mbit sdr, while d2-x signals are related to the 256- or 512-mbit sdr. ai14287 12 d1-a0-a11 d1-dqm0 d1-k v ddf d1-dq0-dq15 nandxxxxnx e f w f al 2 d1-ba0-ba1 d1-ras d2-ras r v ddqd v ddd 16 rb i/o8-i/o15, x16 v ss i/o0-i/o7, x8/x16 13 d2-a0-a12 2 d2-ba0-ba1 cl d2-k d1-ke d2-ke d1-e d d1-w d d2-e d d2-w d d1-cas d2-cas d2-dqm0 d1-dqm1 d2-dqm1 d2-dq0-dq15 16 8
nandxxxxnx description 15/52 table 3. signal names signal function direction nand flash memory i/o0-i/o7 data input/outputs (x8/x16) input/output i/o8-i/o15 data inputs/outputs (x16) input/output al address latch enable input cl command latch enable input e f chip enable input r read enable input rb ready/busy (open- drain output) output w f write enable input wp write protect input v ddf supply voltage power supply v ssf ground ground lpsdram a0-ax address inputs - a10 determines the precharge mode input ba0-ba1 bank select inputs input dq0-dq15 data inputs/outputs (x16/x32) input/output dq16-dq31 data inputs/outputs (x32) input/output dqs0 (1) 1. only available with ddr x32. data read/write strobe for dq0-dq7 input/output dqs1 (1) data read/write strobe for dq8-dq15 input/output dqs2 (1) data read/write strobe for dq15-dq23 input/output dqs3 (1) data read/write strobe for dq24-dq31 input/output k clock inputs input k (2) 2. only available with ddr. clock inputs input ke clock enable input input e d chip select inputs input w d write enable input input ras row address strobe input input cas column address strobe input input dqm0 dq mask enable input controls dq0-dq7 input dqm1 dq mask enable input controls dq8-dq15 input dqm2 (3) 3. only available with sdr/ddr x32. dq mask enable input controls dq16-dq23 input dqm3 (3) dq mask enable input controls dq24-dq31 input ldqs/udqs (4) 4. only available with ddr x16. lower/upper data read/write strobe i/o input/output v ddd supply voltage power supply v ddqd input/output supply voltage power supply v ssqd input/output ground ground v ssd ground ground nc not connected internally du do not use
description nandxxxxnx 16/52 figure 5. tfbga107 connections (top view through package) 1. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. 2. balls shaded in gray are only used for nand and ddr devices. ai10143e v ddd a8 dqm1 v ssd ke a12 dqm0 h a9 d r c dq4 a1 b a3 a 8 7 6 5 4 3 2 1 v ssd v ddqd g f e v ddqd du wp a0 ba0 dq6 v ssqd cas a11 nc w f ba1 a10 du v ddd v ssd 9 nc a2 e d m l k j du dq15 nc dq11 i/o6 v ddqd v ssqd nc dq9 i/o5 dq13 v ddd v ssf v ddf a7 i/o4 i/o7 a5 du du v ssqd a4 du p n 10 nc rb dq2 nc nc e f i/o3 v ddf i/o2 nc cl al dq0 v ssf i/o1 v ssf i/o0 k dq1 dq3 dq5 dq7 v ddd dq10 dq12 dq14 v ssd dq8 du du du du a6 w d nc ras v ddf nc nc k ldqs udqs nc nc nc nc nc nc nc nc nc
nandxxxxnx description 17/52 figure 6. tfbga128 connections (top view through package) 1. only used for ddr. 2. only used for the possible second lpsdram (nandbar3n6). 3. ball u16 is the lpsdram temperature flag. 4. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai13682b h d c b nc a 8 7 6 5 4 3 2 1 dq2 dq4 g f e dq6 nc v ddqd nc nc 9 v ddqd m l k j v ddqd dq10 nc dq0 v ss v ddd al nc dq1 v ddf v ss cl nc nc v ss dq3 v ss dq5 dqm0 dq7 dq9 v ss k k dqm1 dq8 14 13 11 10 12 ba1 a3 ba0 nc nc rb wp nc ras v ss nc a2 a4 nc nc cas e f a0 a1 ke v ddd ke2 (2) n dq12 v ss v ddqd nc i/o1 i/o3 v ss i/o5 i/o7 dq11 dq13 v ddf i/o0 i/o2 nc i/o4 i/o6 nc a7 a8 a6 a5 i/o11 v ss i/o9 v ddf i/o8 i/o10 nc nc nc nc nc 18 17 16 15 r p v u t v ddd v ss dq15 dq14 v ss nc nc nc a11 a10 a12 a9 nc nc a13 nc nc nc nc nc nc nc nc nc i/o13 i/o15 nc i/o12 i/o14 temp (3) v ss w f r w d ldqs (1) udqs (1) e d e d2 (2)
description nandxxxxnx 18/52 figure 7. tfbga137 connections (top view through package) 1. balls shaded in gray are only used for nand and ddr devices. 2. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai13189b v ddqd dqs2 dq20 nc v ssqd k dq9 dq15 h k d r c a7 dq30 b nc v ddd a 8 7 6 5 4 3 2 1 a4 v ssd v ddd a5 g f e a11 du wp dq31 dq29 ke a6 a8 dq26 dqm3 dqm2 dq23 v ssd v ssd w f dq28 v ssqd du cas nc ras 9 nc v ddqd v ddqd a12 v ddd m l k j v ssd i/o2 v ddqd v ddd i/o4 i/o9 ba0 a3 dq4 v ssd dqm0 ba1 w d a1 a2 i/o1 a10 dq6 dq3 nc v ddd v ssd i/o7 i/o14 i/o15 i/o13 v ssqd dqs0 dq5 v ddqd du nc i/o8 e d v ssqd i/o0 du r p n 10 dq12 dqm1 rb dq27 dq22 dq24 e f v ssf dq8 dq2 i/o5 i/o6 dq10 dq13 dqs1 v ssf dq25 dqs3 dq19 v ddf i/o12 dq7 dq1 i/o3 v ddf dq11 dq21 dq16 al a9 dq18 dq17 cl i/o11 a0 dq0 nc i/o10 dq14 v ssqd v ddqd v ddd nc v ddqd du v ssqd v ssqd v ssqd v ddqd v ssqd v ssqd v ddqd v ddqd nc du du
nandxxxxnx description 19/52 figure 8. lfbga137 connections (top view through package) 1. balls shaded in gray are only used for nand and ddr devices. 2. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ni3066 v ddqd dqs2 dq20 e d2 v ssqd k dq9 dq15 h k d r c a7 dq30 b nc v ddd a 8 7 6 5 4 3 2 1 a4 v ssd v ddd a5 g f e a11 du wp dq31 dq29 ke1 a6 a8 dq26 dqm3 dqm2 dq23 v ssd v ssd w f dq28 v ssqd du cas nc ras 9 ke2 v ddqd v ddqd a12 v ddd m l k j v ssd i/o2 v ddqd v ddd i/o4 i/o9 ba0 a3 dq4 v ssd dqm0 ba1 w d a1 a2 i/o1 a10 dq6 dq3 nc v ddd v ssd i/o7 i/o14 i/o15 i/o13 v ssqd dqs0 dq5 v ddqd du nc i/o8 e d1 v ssqd i/o0 du r p n 10 dq12 dqm1 rb dq27 dq22 dq24 e f v ssf dq8 dq2 i/o5 i/o6 dq10 dq13 dqs1 v ssf dq25 dqs3 dq19 v ddf i/o12 dq7 dq1 i/o3 v ddf dq11 dq21 dq16 al a9 dq18 dq17 cl i/o11 a0 dq0 nc i/o10 dq14 v ssqd v ddqd v ddd nc v ddqd du v ssqd v ssqd v ssqd v ddqd v ssqd v ssqd v ddqd v ddqd nc du du
description nandxxxxnx 20/52 figure 9. tfbga149 connections (top view through package) 1. balls shaded in gray are only used for nand and ddr devices. 2. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. 3. for nandbar4n0 and nandbar4n2, the ball e9 is the address a13. ai13231 b dqm1 ke a11 dqm0 h a9 d r c dq4 a1 b a3 a 8 7 6 5 4 3 2 1 g f e du wp a0 ba0 dq6 cas w f ba1 du v ddd 9 nc a7 e d m l k j du dq15 nc dq13 v ssf i/o0 i/o7 du du v ssqd du p n 12 nc rb dq2 nc nc (3) e f i/o2 nc cl al dq0 v ssd i/o1 k dq1 dq3 dq5 dq7 v ddd dq10 v ssqd dq8 du du du du wd nc ras v ddf nc nc nc a10 du a8 du nc du nc v ddqd nc du du du du du du du du du du du du du du 10 11 t r nc du v ssd v ddd du nc i/o6 i/o5 a6 a12 nc nc a2 a5 i/o4 nc nc a4 nc v ddf v ssf nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc i/o3 nc dq11 dq14 dq12 dq9 v ddqd v ssqd i/o9 i/o8 i/o15 i/o14 i/o13 i/o10 i/o12 i/o11 ldqs udqs k
nandxxxxnx description 21/52 figure 10. tfbga152 c onnections - nanda8r3n0, nanda9r3n0, nandb9r3n0 (top view through package) 1. ball b20 is the lpsdram temperature flag. 2. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai13232 h d c b wp a 8 7 6 5 4 3 2 1 v ss dqm0 g f e dq9 v ss dqm1 nc v ss 9 v dd m l k j v dd du dq13 dq0 v ddq dq4 dq5 dq2 v dd dq7 dq3 dq6 dq1 v ddqd nc dq8 ba0 dq10 ba1 dq12 v ss v ddqd du dq14 v ddqd dq11 v ss dq15 14 13 11 10 12 i/o1 nc i/o0 i/o2 v ss nc i/o3 rb du du du i/o4 ke nc al r cl nc i/o5 du nc nc i/o6 i/o7 du du n v ddqd du du du du du du du v ddf v ss du v ss du du du du v ss du v dd ras du e d e f du nc v ss nc nc nc nc nc v ddqd nc 21 20 19 18 17 16 15 r p w v u t aa y du v dd du du du v ss du du du du v ss v dd v ss nc a3 a5 k w d a4 v ss a0 cas a2 a1 v ss nc v ss v dd du du du du temp (1) v ss nc v ddf du v dd du du du du du w f du du v dd v ss a12 a10 a7 a11 a9 a8 a6 v dd
description nandxxxxnx 22/52 figure 11. tfbga152 c onnections - nan dbar3n0, nandb0r3 n0, nandb1r3n0, nanda0r3n0 (top view through package) 1. ball b20 is the lpsdram temperature flag. 2. d1-x signals are related to the 128-mbit sdr, while d2-x signals are related to the 512- or 256-mbit sdr. 3. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai13669b h d c b wp a 8 7 6 5 4 3 2 1 d1- dqm0 g f e d1- dq9 d1- dqm1 nc v ss 9 m l k j d2-k d1- dq0 d1- dq4 d1- dq5 d1- dq2 d1- dq7 d1- dq3 d1- dq6 d1- dq1 v ddqd nc d1- dq8 d1- ba0 d1- dq10 d1- ba1 d1- dq12 nc d1- dq14 v ddqd d1- dq11 14 13 11 10 12 i/o1 nc i/o0 i/o2 nc i/o3 rb d2-a12 d2-a0 d2-a10 d1-ke nc al r cl nc d2-a11 nc nc d2- ba1 n v ddqd nc v ddf d2- dq0 v ss v ddd d1- ras nc e f v ss nc nc nc nc v ddqd nc 21 20 19 18 17 16 15 r p w v u t aa y d2- dq2 d2- dq4 d2- dq3 nc v ss d1-a0 nc nc d2-a1 d2-a3 d2-a4 d2-a2 temp (1) nc v ddf d2-a9 v ddd d2-a5 d2-a7 d2-a8 d2-a6 d2- ras nc v ddd d1-a12 d1-a10 d1-a11 d1-a9 v ddd v ddd v ddqd v ss v ddd v ss v ss v ss d1- dq13 i/o4 i/o5 v ss d1- dq15 i/o6 i/o7 v ddqd v ddd d2- ba0 v ss d2-e d d1-e d d2- dq1 d1-w d d1- cas d2- dq5 d1-k d2- dq6 d2- dq7 d1-a2 d1-a1 d2-w d d2-ke d1-a4 d1-a3 v ddd d1-a5 v ss v ss v ss d2- dqm0 d2- dq8 d2- dq10 d2- dq12 v ss d2- dq14 v ss d1-a8 d1-a6 v ss v ss v ddd d2- dqm1 nc d2- dq9 d2- dq11 d2- dq13 d2- dq15 w f d2- cas d1-a7 v ddd v ss
nandxxxxnx description 23/52 figure 12. tfbga152 (na ndbar3n1) and vfbga152 (n andbar4n5) connections - (top view through package) 1. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. 2. balls shaded in gray are only used for nandbar4n5. ai13669 h d c b dqs1 a 8 7 6 5 4 3 2 1 dqs0 dq5 g f e v ddqd nc dq1 dq11 dq12 9 nc m l k j r f v ss io14 dq14 dq6 v ddqd dq7 dq9 nc v ddqd dq13 dqm1 dq15 v ss dq10 v ss dq3 v ss dq0 dqm0 dq4 nc io13 v ddd v ss dq2 w f io15 14 13 11 10 12 dq30 v ddqd a0 v ss dq24 k v ddd v ss dq29 dqm2 dq26 a2 a6 dq18 v ss a7 k v ss a3 dq25 dq27 dq31 a1 a9 v ddqd v ss n v ddf i/o4 io11 al i/o5 nc v ddf v ss e f io10 io12 i/o6 i/o7 wp v ss v ddf nc nc v ddd v ss a8 a11 nc cl v ddd rb v ss nc dq8 dq17 dq19 dq16 nc 21 20 19 18 17 16 15 r p w v u t aa y i/o2 nc v ddf io8 i/o3 nc io9 v ss i/o1 i/o0 nc nc nc nc ras v ddqd e d a5 ba1 v ss nc a12 cas a4 nc nc nc nc dqs2 v ddd dq21 v ddqd nc nc nc dq28 dqs3 nc dq23 dq22 dqm3 dq20 v ss v ss v ddqd nc nc v ddd ke a10 v ddqd v ddd ba0 v ss w d v ss
description nandxxxxnx 24/52 figure 13. vfbga160 connections - nandbar4n2 (top view through package) 1. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai13190 h d c b nc a 8 7 6 5 4 3 2 1 rb dq0 g f e dq2 v ss v ddqd nc v ss 9 v ddd n m l k udqs v ddqd dq6 nc nc nc nc nc v ss nc nc v ss nc nc nc dq1 dq3 v ss v ss dq5 dqm1 gnd dq7 v ddqd dq4 dqm0 ldqs 14 13 11 10 12 nc r nc w d nc nc nc nc a4 nc nc nc v ddd e f a0 a2 p dq8 v ss v ddd i/o7 i/o1 v ss i/o3 i/o5 v ss dq9 v ss nc i/o0 nc i/o2 i/o4 nc i/o6 ba0 v ss nc nc nc nc v ddf al nc nc cl nc 21 20 19 18 17 16 15 t r y w v u aa dq14 k dq12 dq11 dq15 ke dq13 dq10 v ss v ddqd v ddd nc nc a10 a12 a8 v ddd nc nc nc nc nc nc v ss v ddf nc v ss nc nc nc nc nc nc nc i/o11 nc i/o9 v ss nc i/o8 nc i/o10 i/o15 i/o13 v ss i/o12 nc i/o14 e d ras nc wp nc nc nc a5 v ss nc a1 a3 ba1 22 a11 a13 a9 du nc v ss nc cas w f v ss nc k ab nc v ss nc a6 a7 j
nandxxxxnx signal descriptions 25/52 2 signal descriptions see figure 1 , figure 2 , figure 3 , figure 4 , and table 3 for a brief overview of the signals connected to this device. the following sections further describe the signals. for additional details on the signals, refer to the nand flash memory and the lpsdram datasheets. 2.1 flash memory inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used by the nand flash memory to input the selected address, output the data during a read operation, or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the nand flash memory is deselected or the outputs are disabled. 2.2 flash memory inputs/outputs (i/o8-i/o15) input/outputs 8 to 15 are only available in x1 6 nand flash devices. they are used to output the data during a read operation or input data during a write operation. command and address inputs only require i/o0 to i/o7. the inputs are latched on the rising edge of write enable. i/o8-i/o15 are left floating when the device is deselected or the outputs are disabled. 2.3 flash memory addr ess latch enable (al) the address latch enable activates the latching of the address inputs in the command interface of the nand flash memory. when al is high, the inputs are latched on the rising edge of write enable. 2.4 flash memory command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface of the nand flash memory. when cl is high, the inputs are latched on the rising edge of write enable. 2.5 flash memory chip enable (e f ) the nand flash memory chip enable input activates the memory control logi c, input buffers, decoders, and sense amplifiers. when chip enable is low, v il , the nand flash memory device is selected. if chip enable goes high, v ih , while the nand flash memory is busy, the device remains selected and does not go into standby mode.
signal descriptions nandxxxxnx 26/52 2.6 flash memory read enable (r ) the nand flash memory read enable pin, r , controls the sequential data output during read operations. th e falling edge of r also increments the internal column address counter by one. 2.7 flash memory write enable (w f ) the nand flash memory write enable input, w f , controls writing to the command interface, input address, and data latches. both addres ses and data are latched on the rising edge of write enable. 2.8 flash memory write protect (wp ) the write protect pin is a nand flash memory input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the nand flash memory device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 2.9 flash memory ready/busy (rb ) the ready/busy output, r b , is an open-drain nand flash memory output that can be used to identify if the p/e/r co ntroller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes re ady/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low then indicates that one or more of the memories is busy. 2.10 flash memory v ddf supply voltage v ddf provides the power supply to the internal co re of the nand flash memory device. it is the main power supply for all operations (read, program and erase). 2.11 lpsdram addre ss inputs (a0-ax) the a0-ax address inputs are used by the lpsdram to select the row or column to be made active. if a10 is high (set to ?1?) during read or write, the read or write cycle operation includes an auto precharge cycle. if a10 is low (set to ?0?) during read or write, the read or write cycle does not include an auto precharge cycle. 2.12 lpsdram bank select ad dress inputs (ba0-ba1) the ba0 and ba1 banks select address inputs are used by the lpsdram to select the bank to be made active.
nandxxxxnx signal descriptions 27/52 when selecting the addresses the lpsdram must be enabled, the row address strobe, ras , must be low, v il , the column address strobe, cas , and w must be high, v ih . 2.13 lpsdram data inpu ts/outputs (dq0-dq31) on the lpsdram, dq0-dq31 output the data stor ed at the selected address during a read operation, or are used to input the data during a write operation. dq16-dq31 data inputs/outputs are only available in 32-bit bus width mode. 2.14 lpsdram chip select (e d ) the chip select input e d activates the lpsdram state machine, address buffers, and decoders when driven low, v il . when high, v ih , the device is not selected. 2.15 lpsdram column address strobe (cas ) the column address strobe, cas , is used in conjunction with address inputs a8-a0 and ba1-ba0, to select the starting column location prior to a read or write operation. 2.16 lpsdram row address strobe (ras ) the row address strobe, ras , is used in conjunction with address inputs a11-a0 and ba1-ba0 to select the starting address loca tion prior to a read or write operation. 2.17 lpsdram write enable (w d ) the lpsdram write enable input, w d , controls writing to the lpsdram. 2.18 lpsdram clock input (k) the clock signal, k, is used to clock the re ad and write cycles on the lpsdram. during normal operation, the clock enable pin, ke, is high, v ih . the clock signal k can be suspended to switch the device to the self-refresh, power-down or deep power-down mode by driving ke low, v il .
signal descriptions nandxxxxnx 28/52 2.19 lpsdram clock input (k ) the clock signal, k , is only available on the ddr lpsdra m. it is used in conjunction with the clock signal, k. all lpsdram input signals except dqm0 /dqm1/dqm2/dqm3, udqs/ldqs and dq0- dq31 are referred to the cross point of k rising edge and k falling edge. 2.20 lpsdram clock enable (ke) the clock enable, ke, pin is used by the l psdram to control the synchronizing of the signals with clock signal k. if ke is high, v ih , the next clock rising edge is valid. when ke is low, v il , the signals are no longer clocked and data read and write cycles are extended. ke is also involved in switch ing the device to the self-refresh, power-down and deep power- down modes. 2.21 lpsdram lower/upper data input/output m ask (dqm0 to dqm3) data mask enable inputs, dqm0, dqm1, dqm2, and dqm3 are used to mask the read or write data. dqm2 and dqm3 are only available in 32-bit bus width mode. 2.22 dqs0 to dqs3 input/outputs dqs0 to dqs3 can be either input or output signals and act as write data strobe and read data strobe, respectively. each dqs si gnal corresponds to eight dq pins. 2.23 lower/upper data read/write strobe input/output (ldqs, udqs) ldqs and udqs can be either input or output signals, and act as write data strobe and read data strobe respectively. ldqs and udqs are the strobe signals for dq0 to dq7 and dq8 to dq15, respectively. 2.24 lpsdram v ddd supply voltage v ddd provides the power supply to the internal co re of the lpsdram. it is the main power supply for all operations (read and write). 2.25 lpsdram v ddqd supply voltage v ddqd provides the power supply to the i/o pi ns of the lpsdram and enables all outputs to be powered independently of v ddd . v ddqd can be tied to v ddd or can use a separate supply. it is recommended to power-up and power-down v ddd and v ddqd together to avoid certain conditions that would result in data corruption.
nandxxxxnx signal descriptions 29/52 2.26 ground 2.26.1 nandxxxxnx devices deliver ed in tfbga107/137/149 packages the nand flash memory and lpsdram components have separate grounds, as described below. nand flash v ssf ground v ssf is the reference for the nand flash power supply. it must be connected to the system ground. lpsdram v ssd ground v ssd is the reference for the nand flash power supply. it must be connected to the system ground. lpsdram v ssqd ground v ssqd ground is the reference for the lpsdra m input/output circuitry driven by v ddqd . v ssqd must be connected to v ssd . 2.26.2 nandxxxxnx delivered in tfbga128/152 and vfbga160 packages the nand flash memory and lpsdram components share the same ground v ss , as described below. v ss ground v ss ground is the reference for the power supply for the nand flash and lpsdram components. it must be connected to the system ground.
functional description nandxxxxnx 30/52 3 functional description the nand flash memory and lpsdram components have separate power supplies and, according to in which package they are delivered, they either share the same grounds or have separate grounds. they also have separate control signals, addresses, and data input/outputs, which allows simultaneous access to both devices at any time. figure 14 , figure 15 , figure 16 , figure 17 and figure 18 show the functional block diagrams.
nandxxxxnx functional description 31/52 figure 14. functional block diagram for tfbga107, tfbga137, tfbga149 packages 1. only available in mcp with ddr x16. 2. only available in mcp with ddr x32. 3. only available in mcp with sdr/ddr x32. 4. only available in mcp with ddr lpsdram. v ssd wp nand flash memory v ddf al w d cas ras lpsdram v ddd dqm0 dqm1 ba0-ba1 ai13233c e d i/o0-i/o7, x8 cl e f r w f i/o8-i/o15, x8/16 rb v ddqd a0-a12 k (4) ke v ssqd dq0-dq15, x16/32 dq16-dq31, x32 v ssf udqs (1) ldqs (1) k dqm2 (3) dqm3 (3) dqs0 (2) dqs1 (2) dqs2 (2) dqs3 (2) 8 8 16 2 13
functional description nandxxxxnx 32/52 figure 15. functional block diagram for lfbga137 package 1. only available in mcp with ddr x32. 2. only available in mcp with sdr/ddr x32. 3. only available in mcp with ddr lpsdram. v ssd wp nand flash memory v ddf al w d cas ras lpsdram v ddd dqm0 dqm1 ba0-ba1 ni3067 e d1 i/o0-i/o7 cl e f r w f i/o8-i/o15 rb v ddqd a0-a12 k (3) ke 1 v ssqd dq0-dq15 dq16-dq31 v ssf k dqm2 (2) dqm3 (2) dqs0 (1) dqs1 (1) dqs2 (1) dqs3 (1) 8 8 16 2 13 w d cas ras lpsdram dqm0 dqm1 ba0-ba1 e d2 a0-a12 k (3) ke 2 dq0-dq15 dq16-dq31 k dqm2 (2) dqm3 (2) dqs0 (1) dqs1 (1) dqs2 (1) dqs3 (1) 16 2 13
nandxxxxnx functional description 33/52 figure 16. functional block diagram fo r tfbga128 (nanda9 r3n0, nandb9r3n0), tfbga152 (nanda8r3n0, nanda9r3n0, nandbar3n1, nandb9r3n0), vf bga152 (nandbar4n5), an d vfbga160 packages 1. only available in pop with ddr x16. 2. only available in pop with ddr/sdr x32. 3. only available in pop with ddr lpsdram. 4. only available in mcp with ddr x32. ni3063 ba0-ba1 dqm0 k dq0-dq15 lpsdram v ddqd v ddd 16 a0-a11 ke e d w d cas dqm1 v ddf nand flash memory e f w f al r rb i/o0-i/o7, x8 cl wp ras v ss 8 2 12 dqm2 (2) dqm3 (2) k (3) dq16-dq31 (2) 16 udqs (1) ldqs (1) i/o8-i/o15, x8/16 8 dqs0 (4) dqs1 (4) dqs2 (4) dqs3 (4)
functional description nandxxxxnx 34/52 figure 17. functional block diagram for tfbga152 (nandbar3n0, nandb0r3n0, nandb1r3n0, nanda0r3n0) package ai14288 ba0-ba1 dqm0 k dq0-dq15 128-mbit sdr v ddqd v ddd 16 a0-a11 ke e d w d cas dqm1 v ddf nand flash memory e f w f al r rb i/o0-i/o7 cl wp ras ba0-ba1 dqm0 k dq0-dq15 256- or 512-mbit sdr 16 v ss a0-a12 ke e d w d cas dqm1 ras 8 2 12 2 13
nandxxxxnx functional description 35/52 figure 18. functional block diagram for tfbga128 (nandbar3n6) package ai14288b ba0-ba1 dqm0 k dq0-dq15 512-mbit sdr v ddqd v ddd 16 a0-a12 ke e d w d cas dqm1 v ddf nand flash memory e f w f al r rb i/o0-i/o7 cl wp ras ba0-ba1 dqm0 k dq0-dq15 512-mbit sdr 16 v ss a0-a12 ke e d w d cas dqm1 ras 8 2 13 2 13
maximum rating s nandxxxxnx 36/52 4 maximum ratings stressing the device above the rating listed in table 4: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. table 4. absolute maximum ratings (1) 1. for detailed information on the lpsdram parameters, refer to the m65ka512ab, m65ka512ac, m65kg512ab, m65ka256ag, m65kc512ab, m65kc512ac, m65kd512ac, m65kaxxxaj, m65ka512ah, m65kg512ah, m65kg512ac, m65kgxxxaj, m65kaxxxam, m65kcxxxaj, m65kdxxxaj, and m65kgxxxam datasheets availabl e from your local numonyx sales office. symbol parameter value unit min max t a ambient operating temperature ?30 85 c t stg storage temperature ?55 125 c v io nand flash input or output voltage 1.8 v ?0.6 2.7 v 2.6 v ?0.6 4.6 v v dddq , lpsdram input or output voltage 1.8 v ?0.5 2.3 v v ddf nand flash supply voltage 1.8 v ?0.6 2.7 v 2.6 v ?0.6 4.6 v v ddd lpsdram supply voltage 1.8 v ?0.5 2.3 v i os lpsdram short circuit output current 50 ma
nandxxxxnx package mechanical 37/52 5 package mechanical to meet environmental requirements, numonyx offers these devices in ecopack ? packages. ecopack ? packages are lead-free. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 19. tfbga107 10.5 13 mm - 10 14 active ball array, 0.80 mm pitch, package outline 1. drawing is not to scale. a2 a1 a bga-z24 ddd d e e b se fd fe e1 e sd d1 ball "b1"
package mechanical nandxxxxnx 38/52 table 5. tfbga107 10.5 13 mm - 10 14 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.25 0.010 a2 0.80 0.031 b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.50 10.40 10.60 0.413 0.409 0.417 d1 7.20 0.283 ddd 0.10 0.004 e 13.00 12.90 13.10 0.512 0.508 0.516 e1 10.40 0.409 e0.80??0.031?? fd 1.65 0.065 fe 1.30 0.051 sd 0.40 0.016 se 0.40 0.016
nandxxxxnx package mechanical 39/52 figure 20. tfbga128 - 2-row pe rimeter matrix 2r18 18, 12 12 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. a2 a1 a bga-z87 ddd e b fd e d e1 fe d1
package mechanical nandxxxxnx 40/52 table 6. tfbga128 - 2-row perimeter matrix 2r18 18, 12 12 mm, 0.65 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.10 0.043 a1 0.32 0.013 a2 0.63 0.025 b 0.42 0.37 0.47 0.016 0.015 0.018 d 12.00 11.90 12.10 0.472 0.468 0.476 d1 11.05 0.435 ddd 0.10 0.004 e 12.00 11.90 12.10 0.472 0.468 0.476 e1 11.05 0.435 e 0.65 0.026 fd 0.47 0.019 fe 0.47 0.019
nandxxxxnx package mechanical 41/52 figure 21. tfbga137 10.5 x 13 x 1.2 mm - 10 x 15-13 active ball array, 0.80 mm pitch, package outline 1. drawing is not to scale. e d e b sd a1 a2 a bga-z83 ddd fd d1 e1 e fe ball "b1" table 7. tfbga137 10.5 x 13 mm - 10 x 15-13 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.25 0.010 a2 0.80 0.031 b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.50 10.40 10.60 0.413 0.409 0.417 d1 7.20 0.283 e 13.00 12.90 13.10 0.512 0.508 0.516 e1 11.20 0.441 e 0.80 ? ? 0.031 ? ? fd 1.65 0.065 fe 0.90 0.035 sd 0.40 ? ? 0.016 ? ?
package mechanical nandxxxxnx 42/52 figure 22. lfbga137 10.5 x 13 x 1.4 mm - 10 x 15-13 active ball array, 0.80 mm pitch, package outline 1. drawing is not to scale. e d e b sd a1 a2 a bga-z83 ddd fd d1 e1 e fe ball "b1" table 8. lfbga137 10.5 x 13 x 1.4 mm - 10 x 15-13 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.40 0.055 a1 0.25 0.010 a2 1.00 0.039 b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.50 10.40 10.60 0.413 0.409 0.417 d1 7.20 0.283 ddd 0.10 0.004 e 13.00 12.90 13.10 0.512 0.508 0.516 e1 11.20 0.441 e 0.80 ? ? 0.031 ? ? fd 1.65 0.065 fe 0.90 0.035 sd 0.40 ? ? 0.016 ? ?
nandxxxxnx package mechanical 43/52 figure 23. tfbga149 10 13.5 mm - 12 16 active ball array, 0.80 mm pitch, package outline 1. drawing not to scale. a2 a1 a bga-z78 ddd d e e b se fd fe e1 e sd d1 ball "a1" table 9. tfbga149 10 13.5 mm - 12 16 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.25 0.010 a2 0.80 0.031 b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.00 9.90 10.10 0.394 0.390 0.398 d1 8.80 0.346 ddd 0.10 0.004 e 13.50 13.40 13.60 0.531 0.528 0.535 e1 12.00 0.472 e 0.80 ? ? 0.031 ? ? fd 0.60 0.024 fe 0.75 0.029 sd 0.40 ? ? 0.016 ? ? se 0.40 ? ? 0.016 ? ?
package mechanical nandxxxxnx 44/52 figure 24. tfbga152, 2-row peri meter matrix 2r21 x 21, 14 x 14 x 1.1 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. a2 a1 m3 ddd d e e b fd e1 d1 fe a table 10. tfbga152, 2-row perimeter matrix 2r 21 x 21, 14 x 14 x 1.1 mm, 0.65 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.10 0.043 a1 0.32 0.013 a2 0.63 0.025 b 0.42 0.37 0.47 0.016 0.015 0.018 ddd 0.10 0.004 d 14.00 13.90 14.10 0.551 0.547 0.555 d1 13.00 0.512 e 14.00 13.90 14.10 0.551 0.547 0.555 e1 13.00 0.512 e0.65? ?0.026? ? fd 0.50 0.020 fe 0.50 0.020
nandxxxxnx package mechanical 45/52 figure 25. vfbga152, 2-row pe rimeter matrix 2r21 x 21, 14 x 14 x 0.9 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. a2 a1 m3 ddd d e e b fd e1 d1 fe a table 11. tfbga152, 2-row perimeter matrix 2r 21 x 21, 14 x 14 x 0.9 mm, 0.65 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 0.90 0.035 a1 0.35 0.014 a2 0.45 0.018 b 0.45 0.40 0.50 0.018 0.016 0.020 ddd 0.10 0.004 d 14.00 13.90 14.10 0.551 0.547 0.555 d1 13.00 0.512 e 14.00 13.90 14.10 0.551 0.547 0.555 e1 13.00 0.512 e0.65? ?0.026? ? fd 0.50 0.020 fe 0.50 0.020
package mechanical nandxxxxnx 46/52 figure 26. tfbga152, 2-row perimeter matrix 2r21 x 21, 14 14 x 1.2 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. a2 a1 gx ddd d e e b fd e1 d1 fe a e table 12. tfbga152, 2-row perimeter matrix 2r21 x 21, 14 14 x 1.2 mm, 0.65 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.32 0.013 a2 0.78 0.031 b 0.42 0.37 0.47 0.016 0.015 0.018 d 14.00 13.90 14.10 0.551 0.547 0.555 d1 13.00 0.512 e 14.00 13.90 14.10 0.551 0.547 0.555 e1 13.00 0.512 e 0.65 0.026 fd 0.50 0.020 fe 0.50 0.020 ddd 0.10 0.004
nandxxxxnx package mechanical 47/52 figure 27. vfbga160 15 15 x 1 mm, 0.65 mm pitch, package outline 1. drawing not to scale. a2 a1 a kq_me ddd d e e b se fd e1 d1 sd fe table 13. vfbga160 15 15 x 1 mm, 0.65 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.00 0.039 a1 0.38 0.015 a2 0.51 0.020 b 0.48 0.43 0.53 0.019 0.017 0.021 d 15.00 14.90 15.10 0.591 0.587 0.594 d1 13.65 0.537 ddd 0.10 0.004 e 15.00 14.90 15.10 0.591 0.587 0.594 e1 13.65 0.537 e 0.65 ? ? 0.026 ? ? fd 0.67 0.027 fe 0.67 0.027 sd 0.32 ? ? 0.013 ? ? se 0.32 ? ? 0.013 ? ?
ordering information nandxxxxnx 48/52 6 ordering information table 14. ordering information scheme example: nanda 9 r 3 n 0 a zpa 5 e device type nand flash memory nand flash density a = 1 gbit b = 2 gbits c = 4 gbits dram density 9 = 512 mbits 8 = 256 mbits a = 1 gbit b = 2 gbits 0 = 128 mbits + 512 mbits 1 = 128 mbits + 256 mbits nand flash operating voltage r = 1.7 v to 1.95 v w = 2.5 v to 3.6 v nand bus width 3 = x8 4 = x16 family identifier n = 2112-byte page nand flash dram options 0 = sdr, x16, 133 mhz 1 = sdr, x32, 133 mhz 2 = ddr, x16, 133 mhz 3 = ddr, x32, 133 mhz 4 = ddr, x16, 166 mhz 5 = ddr, x32, 166 mhz 6 = sdr, x16, 166 mhz 7 = sdr, x32, 166 mhz product version a or b or c or d package zbb = tfbga107 10.5 13 mm x 1.2 mm zpc = tfbga128 12 x 12 x 1.1 mm zbc = tfbga137 10.5 x 13 mm x 1.2 mm zcc = lfbga137 10.5 x 13 mm x 1.4 mm zba = tfbga149, 10 13.5 x 1.2 mm zpa = tfbga152, 14 14 x 1.1 mm zqa = tfbga152 14 x 14 x 1.2 mm zpb = vfbga160 15 x 15 x 1 mm zob = vfbga152 14 x 14 x 0.9 mm temperature 5 = ?30 c to 85 c option e = ecopack? package, standard packing f = ecopack? package, tape and reel packing
nandxxxxnx ordering information 49/52 note: devices are shipped from the factory with t he flash memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest numonyx sales office.
revision history nandxxxxnx 50/52 7 revision history table 15. document revision history date version changes 04-jul-2006 1 initial release. 18-sep-2006 2 nandc9r4n0, nanda8r3n0 and nanda9r4n2 added. updated signal names in figure 1: block diagram for tfbga107, tfbga137, and tfbga149 packages , table 3: signal names , figure 9: tfbga149 connections (top view through package) and figure 14: functional block diagram for tfbga107, tfbga137, tfbga149 packages 02-nov-2006 3 nanda9r4n2, nanda9w3n1, nanda 9r3n1 root part number added. tfbga137 10.5 x 13 mm and tfbga160 15 x 15 mm added. section 1: description , section 2: signal descriptions , and section 3: functional description updated accordingly. table 4: absolute maximum ratings updated to add 3v nand flash memory. table 7: tfbga137 10.5 x 13 mm - 10 x 15-13 active ball array, 0.80 mm pitch, mechanical data , figure 7: tfbga137 connections (top view through package) , and figure 13: vfbga160 connections - nandbar4n2 (top view through package) added. table 14: ordering information scheme updated. 06-mar-2007 4 nandbar3n1 root part num ber added. nandb9r4n2 removed. tfbga152 (14 14 1.2 mm) and tfbga128 (12 x 12 x 1.1 mm) added. section 1: description , section 2: signal descriptions , and section 3: functional description updated accordingly. tbias removed from table 4: absolute maximum ratings . 24-july-2007 5 added root part numbers nanda9w4n1, nanda9r4n1, nandb9r4n5, and nanda9r3n2, and references to their respective datasheets. this updated the referenc e that represents the family as nandxxxxnx throughout the document. updated table 2: product list with new root part number information. modified figure 7: tfbga137 connections (top view through package) . changed the lpsdram input or output voltage and supply voltage symbols in table 4: absolute maximum ratings , and updated the information in chapter 6: ordering information . changed nand flash voltage range from 1.8/3 v to 1.8/2.6 v throughout the document. modified figure 5: tfbga107 connections (top view through package) to add three signals. updated figure 14 to add 4-gbit option and notes. also added notes to figure 16 . 16-apr-2008 6 applied numonyx branding. 04-jun-2008 7 added root part numbers nandb0r3n0 and nandb1r3n0 throughout the document. minor text changes. 04-jul-2008 8 added root part numbers nandbar4n0, nandbar4n1 and nandbar4n2 throughout the document.
nandxxxxnx revision history 51/52 06-aug-2008 9 modified datasheet?s title. added root part numbers nandbar4n5, nanda0r3n0, nanda9r3n6, and nandbar4n7 thro ughout the document. removed tfbga160 15 x 15 x 1.2 mm and added vfbga160 15 x 15 x 1 mm packages. 14-aug-2008 10 added nanda9r3n3, nanda9r4n3, nanda9r4n4, nanda9r4n6, and nandbar3n6 root part numbers throughout the document. 23-sep-2008 11 modifed the datasheet?s name in nandxxxxnx. added nandbaw4n1, nandcaw4n1, nandcbr4n3, and nandb9r4n2 root part numbers throughout the document. 01-oct_2008 12 added nandd3r4n5, nanddbr3n5, nandc3r4n5 table 15. document revision history (continued) date version changes
nandxxxxnx 52/52 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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